1. Field
The various embodiments of the present invention relate to second-level interconnect structures, wherein features of the interconnect structure may be altered to achieve desired fine-pitch and low-stress properties, and to methods of making and using the same.
2. Description of Related Art
Interconnects facilitate electrical communication between various electronic components within an electronic system. A “first-level” interconnect, for example, facilitates electrical communication between integrated circuits (“ICs”) and package leadframes. A “second-level” interconnect, for example, facilitates electrical communication between packages and printed circuit boards (“PCBs”).
As the semiconductor industry migrates from two-dimensional ICs to three-dimensional ICs, new second-level interconnect structures that achieve higher electrical performance and successfully integrate heterogeneous ICs are needed. Specifically, new packaging techniques that are cost-effective, thermo-mechanically reliable, and provide compliant and reworkable second-level interconnections from large-body, low thermal coefficient of expansion (“TCE”) packages to PCBs at fine pitches are desirable.
Several second-level interconnect structures are currently used, for example, land grid array (“LGA”) packages, which are assembled onto a socket with flexible pins that contact lands on the package. These sockets are typically assembled onto a PCB with the help of solders. The package is then plugged into the sockets, therefore making it removable and reworkable for processor upgrades. An alternative structure is a solder based assembly that does not require an underfill.
These interconnect structures, however, face fundamental challenges as the trend towards three-dimensional ICs and silicon and glass-based low-TCE interposer packages with fine-pitch board level assembly gains momentum. First, providing a means for stress-relief within the current interconnect structures can be costly. Lower cost options, however, tend to induce tremendous TCE mismatch between low-TCE packages and PCBs. Second, this mismatch subsequently creates fundamental limitations in scaling down the pitch size with traditional solder compositions. Third, current underfill requirements prevent reworkability.
Alternative second-level interconnect structures are thus desirable that address these fundamental limitations and enhance thermo-mechanical reliability without compromising cost, reworkability, or electrical performance.